The present invention relates to a yield analysis tool useful in the production of integrated circuits, as one example, and to such methodology to predict product yield with a given circuit specification in order to increase production yields.
It is essential for integrated circuit (IC) manufacturers to understand the yield behavior of their product lines in order to increase profitability in the face of decreasing selling prices. Statistical methods in combination with simulation programs have been used in the past for providing IC system analysis and characterization in an attempt to predict and/or improve circuit yields.
A typical statistical methodology for characterizing integrated circuits is taught by G. E. Box and N. R. Draper, Empirical Model-building and Response Surface, Wiley, 1987, as an example, and is generally referred to as Response Surface Modeling (RSM). In RSM methodology, certain desired output characteristics of an IC are related to a function of independent variables using known statistical methods. Typically, a designed experiment either by using a simulator or through wafer processing is used to produce a regression equation model to fit a desired circuit characteristic in equation form to the independent variables. For instance, understanding how circuit performance relates to transistor properties and design variables is very valuable since the better these relationships are understood, the more likely a successful match between circuit requirements and IC process capability can be achieved.
The RSM technique provides a picture of the foregoing relationships in a response surface form to allow simple inspection to determine if an acceptable operating point for the circuit exists. The ideal operating target would be located at a midpoint between opposing specification limits in the a parametric space. Parametric space is defined as a multi-dimensional coordinate system with each axis defining one independent variable. Using RSM, a two dimensional response surface can be generated for various outcomes from the generation of regression equations for each of the outcomes desired. As taught by Alvarez, Abdi and Young in their article titled "Application of Statistical Design and Response Surface Methods to Computer-Aided VLSI Device Design, IEEE Trans., on Computer-Aided Design, Vol. 7, 2,1988, the response surfaces can be overlaid to identify if an acceptable operating region exists. Unfortunately, this technique only identifies the existence of such an operating point, but does not translate this into an estimate of yield for the particular circuit. Hence, characterization of new circuits and processes using RSM techniques can identify the existence of a region where all performance limits are satisfied by some combination of transistor properties and design alternatives. However, this technique does not take into account of unavoidable process variations and the effect thereof on actual circuit yields.
Therefore, as will be more fully explained, it is the object of the subject invention to provide a technique for predicting IC yield wherein an empirical relationship between a circuit-level outcome and transistor-level properties can be converted directly into "parametric yield", parametric yield is defined as the proportion of product which is in conformance with all specification limits minus that which fails solely due to unacceptable transistor parametric values. Thus, it is equivalent to the performance-limited yield in an ideal defect free environment.